1. Field of the Invention
This invention pertains in general to a structure to absorb minority charge carriers within an MOS transistor and, more particularly, to buried guard rings to prevent latch-up in a complementary metal-oxide semiconductor ("CMOS") integrated circuit.
2. Description of the Related Art
A CMOS integrated circuit device, by definition, includes at least one p-channel and one n-channel metal-oxide semiconductor field-effect transistor ("MOSFET"). The formation of the MOSFETs leads to the formation of parasitic bipolar junction transistors ("BJTs"). During normal device operations, parasitic transistors are not turned-on and therefore do not affect device operations. However, under certain transient conditions, such as voltage surges, parasitic BJTs may be turned-on and the device is said to be "latched-up."
A parasitic BJT may be turned-on by migrating charge carriers, such as holes to the base, or the n-well region, of a pnp BJT and electrons to the base, or the p-well region, of an npn BJT. Charge carriers can also migrate from the substrate beneath the active regions of the CMOS circuit. In addition, because the collector of a pnp BJT is connected to the base of an npn BJT and the collector of the npn BJT is connected to the base of the pnp BJT, when one parasitic BJT is turned-on by the migrating charge carriers, the other BJT will also be turned on. In addition, if one npn-pnp BJT pair is turned-on, other parasitic BJT pairs in the device will likewise be turned-on, thereby creating a feedback loop within the device. Such a feedback loop consumes power, reduces device speed, and sometimes renders the device inoperative. Once formed, the feedback loop cannot be severed easily. The probability of latch-up increases as device size becomes smaller because undesired charge carriers that create the latch-up triggering current have a greater chance of reaching the areas of the device to trigger latch-up.
Latch-ups may be prevented by stopping the migration of charge carriers or substantially reducing the number of migrating charge carriers. Two known methods have been employed to prevent latch-ups. One method employs "guard rings," or heavily doped p-type material in a p-well and heavily doped n-type material in an n-well that act as "sinks" to divert the undesired minority charge carriers away from the parasitic BJTs. Guard rings are inserted from the surface to form vertical barriers to charge carrier flow and prevent latch-up by reducing the number of electrons and holes that reach critical parts of the CMOS device to trigger latch-up.
The other method places insulating materials in the shallow surface between active regions of the device to act as barriers to carrier charge flow. These insulating barriers are known as shallow trench isolation ("STI") structures.
Because the depth of guard rings and STIs is limited by the fabrication process, charge carriers may still migrate underneath them. Therefore, neither method, by itself or in combination, effectively prevents the flow of carriers to or from the substrate. This charge carrier flow is also known as leakage current.